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Cypress Semiconductor /psoc63 /CSD0 /ADC_CTL

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Interpret as ADC_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADC_TIME0 (OFF)ADC_MODE

ADC_MODE=OFF

Description

ADC Control

Fields

ADC_TIME

ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&2, or as the aperture to capture the input voltage on Cref1&2
ADC_MODE

Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state

0 (OFF): No ADC measurement

1 (VREF_CNT): Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB

2 (VREF_BY2_CNT): Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking)

3 (VIN_CNT): Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data